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functional block diagram rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 16-bit 500 khz wide temperature range sampling adc ad1385 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 16-bit resolution 500 khz sampling rate differential linearity autocalibration specified over C55 8 c to +125 8 c range snr 90 db @ 100 khz (min) thd C88 db @ 100 khz (min) 0.0006% fsr dnl (typ) 0.0015% fsr inl (typ) no missing codes 6 5, 6 10 v bipolar input ranges zero offset autocalibration applications medical imaging cat magnetic resonance radar vibration analysis parametric measurement unit (ate) digital storage oscilloscopes waveform recorders analytical instruments product description the ad1385 is a complete 500 khz, 16-bit, sampling analog- to-digital converter contained in a single package. its differential linearity autocalibration feature allows this high resolution, high speed converter to offer outstanding noise and distortion perfor- mance, as well as excellent inl and dnl specifications, over the full military temperature range. autocalibration effectively eliminates dnl drift over temperature. the ad1385 architecture includes a low noise, low distortion track/hold, a three pass digitally corrected subranging adc, and linearity calibration circuitry. a complete linearity calibration requires only 15 ms. precision thin-film resistors and a propri- etary dac contribute to the parts outstanding dynamic and static performance. the ad1385 uses four power supplies, 5 v and 15 v, and an external 10 mhz clock. power dissipation is nominally 2.76 w. two user selectable bipolar input ranges, 5 v and 10 v, are provided. careful attention to grounding and a single package make it easy to design pcbs to achieve specified performance. the ad1385s pinout is nearly identical to that of the ad1382, a factory calibrated 16-bit, 500 khz sadc. just two additional connections, to e nable and monitor aut ocalibration, are required. this commonality provides an easy upgrade path to extend sys- tem performance and operating temperature range.
rev. 0 C2C ad1385Cspecifications (t a = +25 8 c, v s = 6 15 v, v dd = +5 v, v ss = C5 v, 10 mhz external clock, unless otherwise noted) ad1385kd ad1385td parameter min typ max min typ max units resolution 16 16 bits analog input input ranges 5, 10 5, 10 v input impedance 2.45 2.5 2.55 2.45 2.5 2.55 k w transfer characteristics (combined adc/track/hold) integral nonlinearity 1, 2 , t min to t max 0.0015 0.0015 % fsr 3 differential nonlinearity 1 0.0006 0.0015 0.0006 0.0015 % fsr drift, t min to t max 0.3 0.3 ppm/ c missing codes, t min to t max none none gain error 4 0.05 0.15 0.05 0.15 % fsr drift, t min to t max 8 15 8 15 ppm/ c bipolar zero 4 0.05 0.10 0.05 0.10 % fsr drift, t min to t max 5 15 5 15 ppm/ c psrr 0.006 0.10 0.006 0.10 % fsr/v noise 70 70 m v rms dynamic characteristics 2 5 v fsr, v in = C0.4 db, t min to t max sample rate 500 500 khz signal-to-noise ratio 5 f = 5 khz 90 93 90 93 db f = 100 khz 90 92 90 92 db f = 200 khz 88 91 88 91 db peak distortion f = 5 khz C90 C107 C90 C107 db f = 100 khz C88 C95 C88 C95 db f = 200 khz C82 C88 C82 C88 db total harmonic distortion 6 f = 5 khz C90 C105 C90 C105 db f = 100 khz C88 C95 C88 C95 db f = 200 khz C82 C88 C82 C88 db dynamic characteristics 2 10 v fsr, v in = C0.4 db, t min to t max sample rate 500 500 khz signal-to-noise ratio 5 f = 5 khz 90 95 90 95 db f = 100 khz 90 94 90 94 db f = 200 khz 88 93 88 93 db peak distortion f = 5 khz C90 C108 C90 C108 db f = 100 khz C80 C87 C80 C87 db f = 200 khz C74 C82 C74 C82 db total harmonic distortion 6 f = 5 khz C90 C105 C90 C105 db f = 100 khz C80 C87 C80 C87 db f = 200 khz C74 C82 C74 C82 db digital inputs input voltage v il 0.8 0.8 v v ih 2.25 2.25 v input current 200 200 m a input capacitance 2 2 pf clock frequency 2.5C10 2.5C10 mhz duty cycle 40-60 40-60 % aperture delay 7 77ns digital outputs output voltage v ol @ i ol = 3.2 ma 0.2 0.4 0.2 0.4 v v oh @ i oh = C3.2 ma 2.4 4.5 2.4 4.5 v output capacitance 4 4 pf leakage, outputs disabled 200 200 m a
ad1385kd ad1385td parameter min typ max min typ max units output coding complementary offset binary or complementary twos complement internal reference voltage 9.990 10.010 9.990 10.010 v current 2 5 2 5 ma drift 5 15 5 15 ppm/ c temperature range, case specified 0 +70 C55 +125 c storage C65 +150 C65 +150 c power requirements specified operating range v s 14.25 15.75 14.25 15.75 v +v dd 4.75 5.25 4.75 5.25 v Cv ss C5.25 C4.75 C5.25 C4.75 v current drains +v s 52 80 52 80 ma Cv s 48 75 48 75 ma +v dd 104 160 104 160 ma Cv ss 148 200 148 200 ma power dissipation 2.76 4.125 2.76 4.125 watts notes 1 integral linearity is inferred from ffts. differential linearity is derived from histograms. 2 performance over temperature is specified at the temperature at which the last calibration was performed. 3 fsr = full-scale range. 4 adjustable to zero. 5 snr excludes harmonics 2-9 of the fundamental. 6 thd includes harmonics 2-9 of the fundamental. 7 aperture delay is the time from the rising edge on the hold command input to the opening of the switch in the track/hold. specifications subject to change without notice. timing specifications 1, 2 parameter design minimum typ unit description start command t scs 10 ns setup time t sch 10 ns hold time autozero t azs 10 ns setup time t azh 20 ns hold time data valid t dvs 1.5 cp 3 setup time t dvh 0.5 cp 3 hold time hold command t h 13 cp 3 hold time t d 7 ns delay time data strobe t ds 2cp 3 pulse width t dsd 16.5 cp 3 delay calibrate pulse width 20 ns calibration status 15 ms duration notes 1 refer to figures 17, 18 and 24. 2 design minimums are derived from worst case design analysis and/or simulation results. typical values are based on characterization data. these specifications are not guaranteed or tested. 3 the time duration for this parameter varies in direct proportion to the width of the clock pulse (cp). ad1385 rev. 0 C3C (t a = C55 8 c to +125 8 c, v s = 6 15 v, v dd = +5 v, v ss = C5 v)
ad1385 rev. 0 C4C absolute maximum ratings* +v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v Cv s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C18 v v dd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v ss to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C7 v agnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s reference input . . . . . . . . . . . . . . . . . . . . . . . . . .0 v to +11 v digital inputs . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output short circuit duration reference output . . . . . . . . . . . . . . . . . . . . . . . . . indefinite track/hold output . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 sec digital outputs . . . . . . . . . . . . . . 1 sec for any one output case temperature (operating) . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature model range (case) package option* ad1385kd 0 c to +70 c dh-48a ad1385td C55 c to +125 c dh-48a ad1385td/883b C55 c to +125 c dh-48a *dh-48a = bottom brazed ceramic dip. ad1385 pin connections the ad1385 is housed in a 48-pin bottom-brazed ceramic bathtub package. the pinout is as follows: pin function pin function 1 1 clock in 48 v dd2 (+5 v power) 1 2 power ground 47 power ground 1 3 b1/b9 (msb) 46 v ss2 (C5 v power) 1 4 b2/b10 45 autozero 1 5 b3/b11 44 b1 select 1 6 b4/b12 43 power ground 1 7 b5/b13 42 power ground 1 8 b6/b14 41 cal 1 9 b7/b15 40 gain adjust 10 b8/b16 (lsb) 39 +10 v reference out 11 v dd1 (+5 v signal) 38 Cv s1 (C15 v) 12 power ground 37 signal ground 13 v ss1 (C5 v signal) 36 +v s1 (+15 v) 14 signal ground 35 signal ground 15 data strobe 34 dnc 16 hi/lo byte select 33 dnc 17 oe data enable 32 +10 v reference in 18 start convert 31 v in b 19 hold command out 30 v in a 20 signal ground 29 offset adjust 21 +v s2 (+15 v) 28 cal status 22 hold command in 27 track/h old ou tput 23 Cv s2 (C15 v) 26 signal ground 24 power ground 25 track/hold input dnc = do not connect. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1385 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad1385 rev. 0 C5C figure 4. full-scale sine wave power spectral density, 5 v range, 16384-point fft, 500 khz sample rate figure 5. full-scale sine wave power spectral density, 5 v range, 16384-point fft, 500 khz sample rate figure 6. 100 khz intermodulation performance, 5 v range, 16384-point fft, 500 khz sample rate figure 1. spurious-free range vs. input amplitude, 5 v range, 2048-point fft, 500 khz sample rate figure 2. spurious-free range vs. input amplitude, 10 v range, 2048-point fft, 500 khz sample rate figure 3. full-scale sine wave power spectral density, 5 v range, 16384-point fft, 500 khz sample rate
ad1385 rev. 0 C6C figure 7. 200 khz intermodulation performance, 5 v range, 16384-point fft, 500 khz sample rate figure 8. full-scale sine wave power spectral density, 10 v range, 16384-point fft, 500 khz sample rate figure 9. full-scale sine wave power spectral density, 10 v range, 16384-point fft, 500 khz sample rate figure 10. full-scale sine wave power spectral density, 10 v range, 16384-point fft, 500 khz sample rate figure 11. 100 khz intermodulation performance, 10 v range, 16384-point fft, 500 khz sample rate figure 12. 200 khz intermodulation performance, 10 v range, 16384-point fft, 500 khz sample rate
ad1385 rev. 0 C7C figure 13. ad1385 functional block diagram theory of operation the ad1385 performs conversions using a three-pass subrang- ing technique. this proven circuit concept, implemented with state of the art components, allows the adc, track-hold, and a low noise reference to fit into a single hermetic package, simpli- fying the task of board design. the t/h and adc portions of the ad1385 are distinct circuits with inputs and outputs avail- able on separate pins. this functional division allows greatest application flexibility. the ad1385s major functional blocks are shown in figure 13. the t/h uses a low noise high performance hybrid amplifier and high speed analog switches to achieve precision performance. it operates as an inverting amplifier during track mode. summing junction switch s1 disconnects the analog input to place the cir- cuit into hold mode; the amplifiers output stays constant because the dc path to its inverting input is broken. s1 also grounds the junction of r1 and r2 to minimize signal feedthrough. pedestal is independent of the analog input level because all switching is done near ground. this ensures very low nonlinearity and distortion. a precision reference dac and an 8-bit flash adc form the heart of the ad1385s subranging design. high speed amplifiers combine the analog input and dac output to produce the volt- ages encoded by the flash adc during each pass. a logic array provides all necessary timing, control, and computation. the first rising clock edge after start convert goes high begins the conversion (provided the previous conversion is complete). the hold command goes high and switches the t/h into hold. the held signal from the t/h goes through s2, s3, and error amp 2 to the flash adc. during this pass error amp 2 actually attenuates the adc input to keep the voltage within the flash adcs input range. the flash adc is strobed after a 100 ns settling period. the 8-bit result is saved in the logic array and is routed to the msbs of the reference dac. error amp 1 amplifies the difference between the reference dac output and the held input signal during the second pass. s4 routes this error signal to the flash adc, which is strobed a second time after error amp 1 has settled. the new 8-bit result is used to correct the previous result, increasing the accuracy of this intermediate answer to 13-bit precision. following this the reference dac is updated. both error amplifiers are active during the third pass. s2 is closed, allowing error amp 2 to amplify error amp 1s output. s3 now brings error amp 2s output to the flash adc. the flash adc is strobed a final time after the dac and both error amplifiers have settled. the logic array combines the data from the third flash conversion with the earlier 13-bit word to pro- duce the final 16-bit result. the t/h is returned to track mode, and error amp 2 is reconnected as an attenuator 50 ns after the completion of the third flash conversion to prepare for the next conversion. the output data are placed on the data bus in two 8-bit bytes to be read by the host system. the data strobe output synchro- nizes the data transfer by providing a rising edge for the first byte and a falling edge for the second byte. the hi/lo byte select input allows the user to choose which data byte is pre- sented first. b1 select sets the polarity of the msb to provide either complementary twos complement or complementary off- set binary data. the ad1385s internal linearity calibration capability may be used to compensate for shifts in reference dac linearity with time and temperature. the calibration sequence uses the ad1385s error amplifiers and flash converter to directly mea- sure reference dac linearity errors. the routine calculates the corrections required to each of the reference dacs 8 msbs and stores these in an internal memory; the memory address is determined by the reference dacs codes. the ram data con- trol a correction dac whose output is summed with the refer- ence dacs output. together the two dacs provide the 18-bit linearity required for accurate a/d conversions. calibration corrects only linearity errors, and has a negligible effect on gain and offset errors. a calibration cycle requires 15 ms and may be initiated at any time (see autozero).
ad1385 rev. 0 C8C connection and operation of the ad1385 analog input the analog input should be connected to the track/hold input (pin 25). two pin programmable operating ranges are available: 5 v and 10 v. connect the track/hold output to v in a and/ or v in b as follows: desired scale connect v in a to connect v in b to 5 v track/hold output track/hold output 10 v track/hold output analog signal gnd harmonic distortion is lower when using the 5 v range, while noise is lower when using the 10 v range. the ad1385s noise and distortion performance exceed the capability of most signal sources. maintaining this performance at the system level requires attention to every detail of ground- ing, bypassing, and signal sources. a low impedance high band- width signal source is essential to achieve low distortion. few monolithic amplifiers exist which can maintain signal fidelity at levels comparable with the ad1385s performance, even at low frequencies. high bandwidth means increased noise and de- creased snr. see testing the ad1385 for techniques of achiev- ing the lowest possible noise and distortion. grounding proper treatment of the ad1385s power and ground connec- tions is vital to achieve the best possible system performance. the ideal grounding arrangement is to have a single, solid, low impedance ground plane beneath the device to which all ground and supply bypassing connections are made. this results in the lowest possible ground noise and minimizes undesired interac- tions between the sensitive circuits inside the ad1385. aperture uncertainty, for example, can be degraded by noise in power ground because the hold command signals are referenced to this ground. the digital interface between the ad1385 and the rest of the users system is also critical. the following discussion will help in obtaining optimal performance. these guidelines are general and apply equally well to other high performance analog and digital circuits. the ad1385 must connect to three other parts of the system: the input signal(s), the power supplies, and the digital interface. the system designer must determine the magnitude and type of ground currents and whether they are constant or dynamic. a system block diagram is a valuable aid to understanding how grounds should be connected for good performance. figure 14 shows recommended ground connections for the ad1385 in a typical system. figure 14. ad1385 grounding the ad1385 has a net ground current of about 40 ma. most of this flows in the power grounds. there are also substantial dy- namic currents in the power grounds. the signal grounds have primarily low level static (dc) currents. signal and power grounds are separated inside the hybrid because the resistance and inductance inherent in thick-film construction would cause interactions between ground currents, leading to poor perfor- mance. (remember that an lsb can be as small as 156 m v.) care must be taken to prevent the ad1385s ground currents from flowing in the signal ground between the signal source and the ad1385 if this ground has significant resistance. this is not usually a problem if the signal source is located on the same board as the ad1385 because the resistance can be made very low through the use of a ground plane. the signal sources ground and supply currents must be consid- ered when the source and adc share common power supplies. a ground loop formed by the ad1385, the signal source, and the power supplies can cause significant errors. the connection between the ad1385s ground plane and the systems digital ground is best made away from the ad1385. this will prevent noisy system ground currents from passing through critical parts of the adc. in a very noisy environment it may be wise to isolate the entire analog circuit. figure 14 shows the required isolation provided by a digital buffer. the buffer can then drive resistive and/or capacitive loads without compro- mising ground at the adc. using separate isolated supplies for the adc and signal source will result in a single-point connec- tion between system digital ground and the adcs ground plane at the digital buffer. power supplies and bypassing the ad1385 has four sets of power supply pins. these are: 5 v analog (v dd1 /v ss1 ) 15 v (+v s1 /Cv s1 ) 15 v (+v s2 /Cv s2 ) 5 v power (v dd2 /v ss2 ) a single source may be used to supply like voltages (e.g., v dd1 , v dd2 from the same +5 v supply). each of the four 5 v supply pins should have a distinct low impedance connection to a well-bypassed central source node. this is required because each pin draws large transient currents. these dynamic cur- rents, if passed through a common supply path, would intro- duce crosstalk and increase the ad1385s apparent noise. the two sets of 15 v supplies need not be split in this fashion. every ad1385 supply pin should be bypassed to the ground plane with a high quality ceramic capacitor of 0.01 m f to 0.1 m f. this capacitor should be located as close as possible to the ad1385 to minimize lead lengths. each v dd and v ss pin must also be bypassed to the ground plane with a 10 m f solid tanta- lum bypass capacitor located close to the ad1385. ten micro- farad bypass capacitors for v s2 (pins 21 and 23) are also necessary. these power distribution concepts are shown in figure 15. all power supplies should be of the linear type. switching power supplies are not recommended as they can introduce consider- able high frequency noise into sensitive analog signal paths, de- grading the ad1385s apparent performance. supply pins of equivalent voltage should not be allowed to differ by more than 0.3 v.
ad1385 rev. 0 C9C digital interfaces 10 mhz clock the ad1385 requires a stable external clock. a 10 mhz clock provides a sample rate of 500 kilosamples per second. since the adc operates synchronously with this clock, clock phase noise will appear as jitter in the aperture time. lower clock frequencies may be used, and the sample rate will be reduced proportionately. standard ttl and cmos crystal oscillator modules may be used successfully to generate the required 10 mhz clock signal. these oscillators often create considerable power supply tran- sient noise. the oscillator should be bypassed with both ce- ramic and solid tantalum capacitors using minimum lead lengths. a 10 w resistor in series with the +5 v supply provides additional isolation and low-pass filtering of transients pro- duced by the oscillator. see figure 16. figure 16. isolating clock noise. bypass capacitors should be located close to the oscillator transmission line effects cannot be ignored when supplying the ad1385s 10 mhz clock. the large impedance mismatch be- tween typical pcb traces and the ad1385s cmos clock input can give rise to reflections and high frequency transients when the 10 mhz clock source is located more than a few inches from the ad1385. this noise can corrupt local ground and cause degradation in the ad1385s apparent snr perfor- mance. a series termination resistor of 50 w to 100 w , located at the clock source, will usually eliminate this problem. start convert (pin 18) synchronous operation the start convert signal acts like the data input of a flip-flop. a conversion begins on the first rising clock edge after start con- vert goes high (provided setup time requirements are met). this edge drives hold command out high, switching the t/h into hold mode. hold command out (pin 19) should be connected to hold command in (pin 22) for synchronous operation. continuous conversions at a 500 khz rate may be obtained by holding start convert high. the 10 mhz clock may be divided down and used to drive the start convert input when a lower conversion rate is desired. this will provide clock-synchronized conversions at the lower rate. synchronous conversion timing is shown in figures 17 and 18. start convert may also be used as a gate to capture data in a time window. the rising and falling edges of start convert define the beginning and end of the window during which conversions are desired. some restrictions apply when using a pulse to drive the start convert input. start convert is ignored during a conversion for seven clock periods after hold command out goes low to sig- nal the end of a conversion. the state of start convert is sampled on each rising clock edge, beginning with the seventh edge after hold command out goes low, until a logical high is detected. figure 15. recommended ad1385 power distribution. all 10 m f and 0.01 m f capacitors must have minimum lead length and be located as close as possible to the by- passed pins. make all ground connections directly to the groundplane. if separate ground planes are used for signal and power ground, the supplies should be bypassed as follows: supply bypass to 5 v analog signal ground 15 v (+v s1 /Cv s1 ) signal ground 15 v (+v s2 /Cv s2 ) power ground 5 v power power ground care is also required when using a +5 v powered crystal oscil- lator to provide the ad1385s clock signal. these devices pro duce considerable supply noise and proper bypassing is essential. the oscillator should be bypassed with both ceramic and solid tantalum capacitors using minimum lead lengths. a 10 w resis- tor in series with the +5 v supply provides additional isolation and low pass filtering of transients produced by the oscillator. reference the ad1385 has an excellent internal reference with a typical temperature coefficient of 5 ppm/ c. the reference out (pin 39) is normally connected to reference in (pin 32). an exter- nal reference may be conne cted to the reference input if desired. the reference input pin requires negligible current. the refer- ence input voltage should not exceed +11 v and must remain more positive than 0 v. the reference output requires no by- passing and should not be capacitively loaded. if an external reference is used, it must have low noise to avoid degrading the signal to noise ratio of the ad1385. the reference output can source up to 2 ma of static (dc) cur- rent without affecting the performance of the ad1385. by using the ad1385s internal reference as the system reference, gain error over temperature can be minimized.
ad1385 rev. 0 C10C figure 17. start-convert controlled conversion timing figure 18. free running conversion timing at this point a new conversion will be initiated. the minimum setup and hold times for start convert relative to the rising clock edge are 10 ns. start convert transitions should not be placed in the window which begins 100 ns (one clock period) after the rising edge of hold command out and which ends 1300 ns (thirteen clock periods) after this rising edge (see fig- ure 17). this minimizes internal coupling between start con- vert and sensitive internal circuit nodes. transmission line effects at the start convert input should be considered when designing circuit boards for the ad1385. a se- ries termination resistor of 50 w to 100 w is recommended when the source of start convert is more than a few inches away from the ad1385. this will control reflections and transients which could otherwise degrade the parts performance. asynchronous operation in synchronous operation the t/h is placed into hold mode by the first rising clock edge after start convert goes high. this mode of operation provides maximum rejection of system clock noise. some applications may require the ad1385 to operate asynchronously, that is, with the start convert input directly controlling the track-to-hold transition. this may be achieved using a 2-input or gate connected as shown in figure 19. the rising edge of start convert places the t/h into hold mode; the a/d conversion cycle begins with the first rising clock edge after the start convert transition, and start convert must remain high during at least one rising clock edge in order to begin the conversion. the width of start convert should be either less than 150 ns or greater than 1400 ns to minimize coupling be- tween the falling edge of start convert and sensitive internal nodes. in asynchronous operation the t/h will remain in hold figure 19. connecting the ad1385 to sample the input signal asynchronously from the clock
ad1385 rev. 0 C11C mode as long either hold command out or start convert is high. care is needed in defining system timing to ensure that the t/h has a minimum of 700 ns for signal acquisition before another conversion begins. the minimum width of start con- vert is 20 ns, the sum of t scs and t sch , the minimum setup and hold times. transmission line effects at the start convert and hold com- mand in inputs should be considered when designing circuit boards for the ad1385. a series termination resistor of 50 w to 100 w is recommended when the source of either of these sig- nals is more than a few inches away from the ad1385. this will control reflections and transients which could otherwise degrade the parts performance. output data the output data are multiplexed in two bytes onto an 8-bit data bus. data are guaranteed to be stable at the time of the edges of data strobe (pin 15). hi/lo byte select (pin 16) controls which byte is presented first. if hi/lo byte select is high, then byte0 is b9Cb16 and byte1 is b1Cb8. the order of the data bytes is interchanged when hi/lo byte select is low. byte 0 and byte 1 are defined in the timing diagram figure 17. b1 is the most significant bit of the reconstructed 16-bit data. b1 select (pin 44) determines whether data is presented in complementary twos complement or complementary offset bi- nary form. complementary twos complement data is provided when b1 select is low. oe may be used to place the data bus into a high impedance state. the arithmetic unit in the ad1385 saturates at all 0s or all 1s if the input range is exceeded. table i. b1 select 0 1 complementary twos complementary offset data format complement binary Cfull-scale data 7fffh ffffh 0 v data ffffh 8000h +full-scale data 8000h 0000h calibration (pins 28 and 41) calibration corrects for linearity errors in the reference dac arising from internal component mismatches or temperature changes. it has a negligible effect on gain and offset errors, and these should be corrected by other means. the ad1385 must be calibrated after power-up, and recalibration is recommended whenever the parts temperature has changed by more than 15 c. performance degrades gracefully with temperature changes, resulting in small but gradual decreases in snr and increases in distortion which may be eliminated by recalibra- tion. calibration codes are stored in internal ram and are lost when power is removed. figures 20C22 show the effects of uncalibrated versus calibrated operation. figure 20. full-scale power spectral density after power- up at t case = +25 c without calibration, 5 v range, 16384-point fft, 500 khz sample rate. compare with figure 4. figure 21. full-scale power spectral density at t case = +125 c, calibration performed at t case = +25 c, 5 v range, 16384-point fft, 500 khz sample rate figure 22. same as figure 21 following recalibration at t case = +125 c
ad1385 rev. 0 C12C no external switches or relays are required for calibration and all connections to the ad1385 may remain in place. the track/hold is internally isolated from the analog input by ana- log switches and used as a buffer during the calibration process. its signal output (pin 27) must remain connected to the a/d input(s) (pin 30 and/or pin 31, as appropriate) for successful calibration. hold command out (pin 19) must also remain connected to hold command in (pin 22), either via direct con- nection (synchronous sampling) or with an external or-gate (asynchronous sampling, figure 19). a calibration sequence may be initiated at any time by bringing the cal input (pin 41) low. the calibration request remains pending if a conversion is in process, and calibration begins on the first rising clock edge after the end of that conversion. cali- bration begins on the first rising clock edge after cal is as- serted if the ad1385 is idle when calibration is requested. the minimum pulse width for the cal input is 20 ns. the cal in- put has priority over the start convert signal in all cases. the cal status output (pin 28) goes high as soon as calibra- tion begins and remains high until the calibration cycle is com- pleted. pulsing cal low while cal status is high has no effect. a full calibration requires about 15 ms with a 10 mhz clock and proportionately longer with slower clocks. calibration has no effect on the contents of the autozero regis- ter. the apparent zero point may shift a few lsbs as a result of the calibration. autozero after recalibration will provide the greatest possible accuracy (see autozero). the ad1385 controller allocates 17 clock periods after the con- clusion of a calibration cycle for track/hold recovery and signal acquisition. activ ity at the start convert input during this inter val is ignored. figure 23 shows the timing associated with the resumption of synchronous conversions following a calibra- tion cycle. start-convert should remain low during the calibration period when using asynchronous sampling (figure 19). figure 23. resumption of synchronous conversions following completion of calibration the cal input may be held low indefinitely, causing repeated calibration cycles. the ad1385 will complete the calibration in progress when cal goes high and will then begin normal con- versions after the 17-clock-period delay. this simplifies the system-level implementation of the power-up reset function. the ad1385 requires a 5 minute warmup to reach thermal equilibrium after power is applied, and calibration may drift slightly during this time. occasional recalibration will provide a slight improvement in distortion and noise performance during warmup. autozero (pin 45) the autozero function may be used to digitally correct internal offsets in the track/hold and adc as well as external offsets. to use autozero the track/hold input must be connected to a zero reference prior to the zeroing conversion. this connection is external to the ad1385 and must be provided by the user; the resistance of this connection is not critical but should be less than 1000 w . an autozero cycle forces the ad1385s digital output to indicate exactly zero when its input is at the zero point, nominally 0 v. (this assumes that the complementary twos complement data format is used. autozero forces the digi- tal output to midscale when the selected data format is comple- mentary offset binary.) autozero operates by storing the digital result of a zeroing conversion and subtracting it from all subse- quent conversion results. this reduces the maximum nonsat- urating input of the ad1385 a small amount at one end of its range depending on the magnitude and polarity of the offset. the autozero feature is enabled by driving the autozero input (pin 45) low before a falling edge at the data strobe output. offset data will be stored on the first rising edge of data strobe after autozero is brought high; the offset data are also available on the ad1385s data bus during this data strobe pulse. au- tozero operation is illustrated in figure 24. all subsequent a/d conversions will be digitally corrected by the offset term as long as autozero remains high. the offset register is cleared when autozero goes low and the contents of the data output registers will revert to their uncorrected value. figure 24 shows autozero timing requirements. autozero cannot be activated until the first conversion after power-up has been completed. the autozero feature may be disabled by keeping autozero low. figure 24. autozero cycle operation
ad1385 rev. 0 C13C gain adjust (pin 40) the internal reference of the ad1385 may be adjusted by vary- ing the voltage applied to the gain adjust pin. the input im- pedance of this pin is nominally 20 k w , with a tolerance of 20%. a change of 1 v on pin 40 will change the reference volt- age by about 10 mv. the reference may be adjusted by 150 mv without degr ading the ad1385s performance. the simplest method of implementing the gain adjust is to connect a potenti- ometer between the 15 v supplies, with the wiper connected to the gain adjust pin. care should be taken to ensure that noise does not enter the adc through the gain adjust pin. figure 25a. ad1385 gain adjust circuit offset adjust (pin 29) the adcs offset voltage may be adjusted by means of a voltage applied to the offset adjust pin. the nominal adjustment sensi- tivity is 0.005% fsr/v. the input impedance is 20 k w with a 20% tolerance. the simplest way to implement the offset ad- just is to connect a potentiometer between the 15 v supplies, with the wiper connected to the offset adjust pin. care should be taken to ensure that noise does not enter the adc through the offset adjust pin. figure 25b. ad1385 offset adjust circuit applications mounting and thermal considerations the ad1385s operation is specified over a case temperature range of C55 c to +125 c. case temperature in still air is nor- mally about 20 c above ambient, and a heat sink and/or air flow is required to guarantee specified performance when high ambi- ent temperatures are expected. a thin heat transfer plate, mounted beneath the package to conduct heat into the ground plane, may be sufficient. this plate may be made of metal pro- vided care is taken to prevent shorting the package pins. an excellent alternative is to use an elastomeric heat conducting material. these materials will conform to the board and to the ad1385 package to improve heat transfer while reducing me- chanical stress. elastomeric materials normally will not require thermally conductive grease. testing the ad1385 it is difficult to test the ad1385 with ordinary test methods be- cause of the parts very low distortion and noise. the number of output codes and the nature of the analog to digital conversion make static tests of performance especially cumbersome. sub- ranging converters with error correction circuitry can have flaws at any place in their transfer function and all codes must be ex- ercised for a complete test. histograms provide a convenient way to measure all codes in a modest amount of time. even histograms can be slow, when 20 million conversions (40 seconds) may be required to achieve statistically valid results. dynamic tests based on ffts are the most powerful. they quantify noise and distortion as a function of input frequency. from them one can infer qualitative integral and differential nonlinearity performance while determining the adcs specific dynamic performance. ffts are especially useful for systems which require excellent dynamic response, such as magnetic resonance imaging. they also uncover performance problems that dont show up in static tests of linearity. the difficulty in doing fft tests stems from the requirement for ultra pure sine wave inputs at various frequencies over the operating bandwidth of the adc. even the best available gen- erators are not capable of supplying signals with sufficiently low noise and low distortion for testing the ad1385. few generators permit phase-locking to the adc clock. (phase-locking makes it possible to obtain an integral number of cycles of the input sine wave within the fft data window, which in turn eliminates the need for windowing functions and the spectral spreading they cause.) the best generator currently available for this purpose is the br uel and kjaer model 1051 (or 1049). this generator provides a programmable output frequency up to 250 khz with better than 0.001 hz resolution. the generators distortion perfor- mance at frequencies below 20 khz is better than the ad1385 but degrades at 100 khz and higher. noise is a problem at all frequencies, being about C85 db over the ad1385s bandwidth. both noise and distortion can be reduced to acceptable levels with filters. passive narrow bandwidth filters will reduce har- monic distortion to less than C100 db. inductors wound on large pot cores with air gaps can be made quite linear, and with careful winding will provide low loss and low capacitance. such filters will reduce noise to negligible levels outside their pass band to provide a much better view of actual adc performance. the effect of aperture jitter, for example, cannot be observed without a filter. the ffts shown in figures 3-12 were produced using these methods. these tests are done as a normal part of production testing to guarantee the dynamic performance of the ad1385. multiplexing and high impedance inputs multiplexing the ad1385s input presents several challenges in component selection. the on-resistance of most available mul- tiplexers and switches is a function of the applied voltage. this, coupled with the ad1385s 2.5 k w input resistance, can intro- duce significant harmonic distortion unless the multiplexer out- put is buffered. all monolithic switches and multiplexers exhibit this behavior to some extent, with cmos-based designs gener- ally worse than those using jfet technology. an acceptable alternative is the dg180 family produced by siliconix. these hybrid switches use discrete jfet pass devices to provide an extremely low on-resistance virtually indepen- dent of signal level. care should be taken to match the switchs common-mode signal capability with operating range desired for the ad1385. the finite on-resistance of any unbuffered switch driving the ad1385 will introduce a gain error, and that error may change appreciably over temperature.
ad1385 rev. 0 C14C buffering the multiplexers output will eliminate the problems caused by its on-resistance. the choice of buffer depends on the nature of the systems input signals. there are two cases to consider: static inputs and dynamic inputs. static applications amplifier noise, cmrr linearity, and settling time are of pri- mary importance when the inputs are low frequency or dc. this is the case in a cat-scan imager, for example, when sig- nals are produced by integrating photocurrents. noise limits ultimate system resolution. the ad1385 has a typical input- referred noise of 70 m v rms. buffer noise must be added to this in a root-sum-squares fashion to determine total system noise. a buffer amplifier which adds noise of 18 m v rms, for example, will result in a system noise level of (18 2 +70 2 ) 1/2 = 72 m v rms, a negligible increase. detailed system noise calculations require knowledge of the buffers noise spectral density and equiva- lent noise bandwidth. the ad1385s equivalent noise band- width is 2.2 mhz. low noise electronic design (c.d. motchenbacher and f.c. fitchen, john wiley and sons, new york, 1973) provides excellent discussions of noise analysis and calculations. buffer amplifier cmrr produces only gain error as long as the value of cmrr is independent of signal level. the size of this gain error is directly related to the actual value of cmrr; an amplifier with 60 db cmrr will create an apparent gain error of 0.1%. the precise value of cmrr is not critical as long as it remains independent of signal level. any variation in cmrr with input level will introduce nonlinearity. the smaller the value of cmrr (in db), the more critical variations in this value become. an amplifier with cmrr ranging from 100 db to 110 db over the range of C10 v to +10 v will produce negligible nonlinearity, while an amplifier whose cmrr varies from 60 db to 70 db over the same range would be completely unacceptable. buffer settling time will affect the systems throughput. the sys- tem sample rate can be maintained at 500 khz provided the buffers settling time is less than about 1.7 microseconds. the input channel should be switched just after the ad1385s sha enters hold mode as indicated by a rising edge at hold com- mand in (pin 22). dynamic applications dynamic applications complicate the choice of buffer amplifier. the amplifiers harmonic distortion performance now becomes as important as its noise, cmrr linearity, and settling behavior. few manufacturers specify amplifier thd in the noninverting configuration. these specifications, when available, seldom ad- dress signals greater than 10 v p-p or frequencies above 1 khz. it may be necessary to characterize candidate amplifiers from several vendors to find the best fit to the amplitude and fre- quency requirements of a particular application. such evalua- tions are easily performed using a spectrum analyzer. a notch filter tuned to the fundamental frequency greatly improves mea- surement resolution. it is also possible to use the ad1385 as the measuring device by performing ffts on the output data. refer to the discussion of signal sources in testing the ad1385. unipolar operation the ad1385 does not provide a direct unipolar input capabil- ity. unipolar inputs can be achieved using the circuits of fig- ures 26 and 27. the circuit in figure 26 is suitable when a low input impedance is acceptable. the ad845 is an excellent am- plifier choice for this application. multiplexed applications should use the circuit of figure 27. the discussions under high impedance inputs also apply to amplifier selection for high impedance unipolar operation. figure 26. unipolar-to-bipolar conversion (low input impedance) figure 27. high input impedance unipolar-to-bipolar conversion circuit data bus interface the ad1385s data outputs are 4 ma cmos drivers and are not intended to be connected directly to a system data bus. charging and discharging a capacitive data bus creates large supply transients and ground spikes which can interfere with the ad1385s operation and result in erroneous data. registers and/or buffers should be used to isolate the ad1385 from the bus. buffering devices should be located close to the ad1385 to minimize the capacitive load presented to the converters data outputs. control will be simplified by permanently grounding the ad1385s oe input when using buffers. a schematic of a typical 16-bit bus interface is shown in figure 28.
ad1385 rev. 0 C15C figure 28. basic ad1385 digital interface (16-bit complementary 2s complement data, autozero not used, other digital and analog inputs not shown) the layout accommodates buffer amplifiers with standard op amp pinouts in both 14- and 8-pin dip packages. the pin numbers shown for u12 in figure 29 refer to the 14-pin format. an 8-pin op amp such as the ad845 should be positioned with package pin 4 inserted in layout pin 6. the ad845 provides slightly better distortion performance than the ad842, an am- plifier in a 14-pin package, with no significant increase in noise. sample board layout figures 29-34 show the layout of an evaluation board for the ad1385. this layout incorporates the grounding, power distri- bution, and interface concepts described in previous sections. this 4-layer layout makes extensive use of ground and power planes and provides optimal ad1385 performance.
ad1385 rev. 0 C16C figure 29. ad1385 evaluation board schematic
ad1385 rev. 0 C17C figure 30. ad1385 evaluation board layout, layer 1 (component side) figure 31. ad1385 evaluation board layout, layer 2 ( 15 v planes)
ad1385 rev. 0 C18C figure 32. ad1385 evaluation board layout, layer 3 ( 5 v planes) figure 33. ad1385 evaluation board layout, layer 4 (solder side)
ad1385 rev. 0 C19C figure 34. ad1385 evaluation board silkscreen
ad1385 rev. 0 C20C outline dimensions dimensions shown in inches and (mm). 48-pin bottom brazed ceramic dip (dh-48a) c1579C10C4/92 printed in u.s.a. ad1385 evaluation board parts list qty. ref. des. description (manufacturer/pn) 1 c1 ceramic capacitor, 10 pf, 50 v (mallory cec100j) 13 c2, c3, c6, c7, c11, tantalum capacitor, 10 m f, 35 v c12, c21, c22, c26, (mallory tdl106k035s1d) c27, c29Cc31 16 c4, c5, c8Cc10, ceramic cap, 0.1 m f, 100 v(murata c13Cc20, c23Cc25 erie rpe122z5u104m100v) 2 c28, c32 tantalum capacitor, 39 m f, 10 v (kemet t110b396k010as) 4 cr1Ccr4 1n4001 diode 3 j7, j13, j14 bnc female, pc mount (pomona 4578) 8 jmp2Cjmp6, jmp8, jumper, 2 position (3m 929950-00) jmp9, jmp13 3 r1, r5, r6 rn55c resistor, 2.00k 2 r2, r3 50k 20-turn trimpot* (bourns 3299w-1-503) 2 r4, r8, r9 rn55c resistor, 10.0k 1 r7 carbon composition resistor, 100 w , 1/2 w 1 r10 rn55c resistor, 10 w 1 sw1 momentary spst, c & k ks l l-r2-c-q 1 u7 74als74 1 u9 ad1385kd (analog devices) 2 u10, u11 74als574 1 u 12 ad845kn (analog devices) 1 u13 10 mhz dip crystal oscillator 1 u14 74als04 1 u15 74als32 2 socket strip (spc mps1p-32-gg) 1 pin strip (3m 929647-01-36) 1 socket, 14-pin oscillator (augat 504-ag10d) 4 socket, 14-pin (augat 514-ag11d) 2 socket, 20-pin (augat 520-ag11d) 2 ejector latch (3m 3505-3) 1 50-pin connector (3m 3433-5002) 2 screw, 2-56 1/2 2 hex nut, 2-56 *trimpot is a trademark of bourns.

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